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Juste publié ! Intel® Xeon Phi™ Coprocessor High Performance Programming 
Apprenez les fondements de la programmation pour cette nouvelle architecture et les nouveaux produits. Nouveau !
Intel® System Studio
Intel® System Studio est une suite exhaustive d’outils intégrés de développement de logiciels qui peut accélérer la mise sur le marché, renforcer la fiabilité des systèmes et améliorer l’efficacité énergétique et les performances. Nouveau !
Au cas où vous l’avez manqué – Rediffusion du webinaire en direct de deux jours
Introduction au développement d’applications hautes performances pour processeurs Intel® Xeon® et coprocesseurs Intel® Xeon Phi™.
Structured Parallel Programming
Les auteurs Michael McCool, Arch D. Robison et James Reinders utilisent une approche basée sur des modèles structurés qui devrait rendre le sujet accessible à tous les développeurs de logiciels.

Optimisez les performances de vos applications grâce à la programmation parallèle et avec l'aide des ressources novatrices d'Intel.

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Intel® Parallel Studio

Intel® Parallel Studio, qui apporte aux développeurs Microsoft Visual Studio* C/C++ un traitement parallèle de bout en bout simplifié, fournit des outils avancés permettant d’optimiser les applications clientes pour un traitement multicœur et à nombreux cœurs.

Produits Intel® de développement logiciel ›

Explorez tous les outils qui vous aideront à optimiser vos applications pour l’architecture Intel. Certains outils sont disponibles pour une période d’évaluation gratuite de 45 jours.

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Trouvez des guides et des informations d'assistance sur les outils Intel.

Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness
Par Indraneil Gokhale (Intel)Publié le 09/15/20140
As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspects of their workloads: Vectorization/code generation Thread parallelism This article mainly talks a...
Improve Server Application Performance with Intel® Advanced Vector Extensions 2
Par Thai Le (Intel)Publié le 04/30/20150
The Intel® Xeon® processor E7 v3 family now includes an instruction set called Intel® Advanced Vector Extensions 2 (Intel® AVX2), which can potentially improve application performance related to high performance computing, databases, and video processing. To validate this statement, I performed a...
Accelerating Financial Applications on Intel® architecture
Par George Raskulinec (Intel)Publié le 04/29/20150
Download PDF Accelerating Financial Applications on Intel Architecture [PDF 575.55KB] Download File QuantLib_optimized_for_IA.tar.gz [TAR 522.48KB] Abstract:   A paper titled Accelerating Financial Applications on the GPU compared GPU vs. CPU performance using four QuantLib library financial ...
Introducing Batch GEMM Operations
Par Zhang Z (Intel)Publié le 04/28/20150
The general matrix-matrix multiplication (GEMM) is a fundamental operation in most scientific, engineering, and data applications. There is an everlasting desire to make this operation run faster. Optimized numerical libraries like Intel® Math Kernel Library (Intel® MKL) typically offer parallel ...
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[Acceler8 '12] Scaling fast sequential algorithms using MapReduce
Par seviyor Publié le 30/05/12 0
Parallel algorithm vs. work in parallel As many of the forum posts have shown, fast algorithms for solving the problem of maximal common substrings gave good results on the benchmarck but didn't really scale with the number of threads. This is because those sub-square (linear or n*logn) algorithm...
Create a Ubuntu 11.04 LiveUSB to use Intel® Parallel Studio XE
Par Xavier H. (Intel) Publié le 14/05/12 0
You need a license for Intel® Parallel Studio XE for Linux and and at least a 4GB USB Key. Get an ISO image of Ubuntu 11.04. Create a new Ubuntu 11.04 LiveUSB, with persistence mode enabled (you can specify a size of 1mo for the persistence file, you will overwrite it with a ~3Go file in the next...
Getting system parameters in order to improve data structures
Par andreib Publié le 13/05/12 0
Dear programmer, there are a lot of situations when you have to deal with very efficient data structures to get a good performance. An important characteristic of a data structure is granularity. How big the data structure should be? Which is the optimum size of its elements? Of course there is ...
Retour d'expérience concours Acceler'8
Par Maxime RIVIERE Publié le 01/02/12 1
La nouvelle édition du concours acceler'8 a pris fin il y'a un peu plus d'un mois. Contrairement au concours précédent, nous n'avons pas publié d'article. Il faudrait que nous le fassions à l'occasion. C'etait une part intéressante du concours précédent. Les contraintes de la vie courante reprenn...
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Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
Par kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Haswell Transactional Memory read/write-set information
Par YangHun P.0
Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX). As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly) Then, Can I track transactional memory operations and get information like address, and values of read/write-set?
I have a problem with igzip
Par gq L.0
Hi! I am studying about compression algorithm and software. I have question about igzip. I download igzip library in intel homepage. But I don`t know how to make wrapper. Can you send me 'example of wrapper' or 'example code' or 'manual'? I read homepage and saw a simple application. I don`t know how to input target file for compression and to output compression file and how to decompression? Do I make code about 'fast_lz and init_stream' function by myself? Plz help me. thank you
PCM reporting lower than expected memory read counts
Par Patrick L.2
I have a piece of code on which I'm running PCM (Performance Counter Monitor). It is essentially the following: uint64_t *a,*b; a = new uint64_t[LEN]; b = new uint64_t[LEN]; for( int i=0;i<LEN;i++ ) a[i] = b[i];With LEN set to 402,653,184 (384 Mi), PCM is reporting 0.72 GB under READ and 6.30 GB under WRITE. Given that each array is 3 GiB, I would expect that both arrays would be read (since processor uses write-allocate), giving a READ of about 6 GiB. I would expect array "a" to be written back, giving a write count of 3 GiB. Does anyone know why the read count is so low, and the write count is higher than expected? Processor is Intel Core i7 940 (Nehalem). Any help is appreciated. Patrick
igzip 'make' problem
Par gq L.1
Hi   I download igzip_042.zip and modify YASM path of Makefile   but it doesn`t make .exe file   I don`t know igzip execution sequence   If you have document about igzip, plz share it.   Thank you
igzip 'make' problem
Par gq L.0
Hi I download igzip_042.zip and modify YASM path of Makefile but it don`t make .exe file I don`t know igzip execution sequence If you have document about igzip, plz share it. Thank you
error when compile parsec with icc.
Par sun l.0
error when compile http://parsec.cs.princeton.edu/parsec3-doc.htm with icc. What's "/opt/intel/cc/latest"? it doesn't exist on my machine. should i make a cc fold? ---------- [root@amax parsec-3.0]# cd /opt/intel [root@amax intel]# ls bin                     composerxe  ism       mic     cnc                     impi        lib       mkl     include     licenses  mpi-rt     ipp         man       tbb [root@amax parsec-3.0]# whereis icc icc: /opt/intel/bin/icc [root@amax parsec-3.0]# whereis cc cc: /usr/bin/cc --------------  some config of icc.bldconf # CC_HOME is the installation root of the C compiler   export CC_HOME="/opt/intel/cc/latest"   #  export CC_HOME="/opt/intel/bin/" when i changed CC_HOME to "/opt/intel/bin/", still error     ----------- [root@amax parsec-3.0]# parsecmgmt -a build -c icc [PARSEC] Packages to build:  blackscholes bodytrack facesim ferret freqmine raytrace swaptions fluidanimate vips x264 canneal dedup streamcluster [PARSEC] [========== Build...
Parallel Image Processing in OpenMP - Image Blocks
Par Royi5
Hello, I'm doing my first steps in the OpenMP world. I have an image I want to apply a filter on. Since the image is large I wanted to break it into non overlapping parts and apply the filter on each independently in parallel. Namely, I'm creating 4 images I want to have different threads. I'm using Intel IPP for the handling of the images and the function to apply on each sub image. I described the code here: http://stackoverflow.com/questions/29319226/parallel-image-processing-in... The problem is I tried both sections and parallel for and got only 20% improvement. What am I doing wrong? How can I tell each "Worker" that though data is taken from the same array, it is safe to read (Data won't change) and write (Each worker has exclusive approach to its part of the result image). Thank You.
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